
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:52:10 02/03/2011
-- Design Name:   ALU
-- Module Name:   E:/alu/tb_alu.vhd
-- Project Name:  alu
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE WORK.LCSE.all;
--USE WORK.LCSE_test.all;

ENTITY tb_alu_vhd IS
END tb_alu_vhd;

ARCHITECTURE behav OF tb_alu_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ALU
	PORT(
		Reset : IN std_logic;
		Clk : IN std_logic;
		u_instruction : alu_op;    
		Databus : INOUT std_logic_vector(7 downto 0);      
		FlagZ : OUT std_logic;
		FlagC : OUT std_logic;
		FlagN : OUT std_logic;
		FlagE : OUT std_logic;
		Index_Reg : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL Reset :  std_logic := '0';
	SIGNAL Clk :  std_logic := '0';
	SIGNAL u_instruction : alu_op;

	--BiDirs
	SIGNAL Databus :  std_logic_vector(7 downto 0);

	--Outputs
	SIGNAL FlagZ :  std_logic;
	SIGNAL FlagC :  std_logic;
	SIGNAL FlagN :  std_logic;
	SIGNAL FlagE :  std_logic;
	SIGNAL Index_Reg :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ALU PORT MAP(
		Reset => Reset,
		Clk => Clk,
		u_instruction => u_instruction,
		FlagZ => FlagZ,
		FlagC => FlagC,
		FlagN => FlagN,
		FlagE => FlagE,
		Index_Reg => Index_Reg,
		Databus => Databus
	);

	DATABUS <= "00000000","00000001" after 10000 ns,
				  "00000010" after 20000 ns,
				  "00000011" after 30000 ns,
				  "00000100" after 40000 ns;
	 
	 CLOCKING:process
   begin
		Clk <= '1', '0' after 25 ns;
		wait for 50 ns;
   end process;

   process
   begin
      Reset           <=  '1', '0' after 10 ns, '1' after 35 ns;
		
		u_instruction   <= nop, op_lda after 10000 ns, 
			   op_ldb after 20000 ns, 
			   op_ldacc after 30000 ns, 
			   op_ldid after 40000 ns, 
			   op_mvacc2id after 46000 ns, 
			   op_mvacc2a after 50000 ns, 
			   op_mvacc2b after 54000 ns, 
			   op_add after 58000 ns, 
			   op_shiftr after 62000 ns, 
			   op_add after 64000 ns,
				op_shiftl after 66000 ns, 
			   op_sub after 70000 ns, 
			   op_and after 74000 ns, 
			   op_or after 78000 ns, 
			   op_xor after 82000 ns, 
            op_cmpe after 86000 ns,
	  		   op_cmpl after 90000 ns, 
			   op_cmpg after 94000 ns, 
			   op_ascii2bin after 98000 ns, 
			   op_bin2ascii after 102000 ns,
			   op_oeacc after 106000 ns;

      wait for 250000 ns;
      


     
--	  u_instruction   <= nop, op_lda after 100 ns, 
--								op_ldb after 200 ns, 
--								op_ldacc after 300 ns, 
--								op_ldid after 400 ns, 
--								op_mvacc2id after 600 ns, 
--								op_mvacc2a after 800 ns, 
--								op_mvacc2b after 1000 ns, 
--								op_add after 1200 ns, 
--								op_shiftr after 1400 ns, 
--								op_shiftl after 1600 ns, 
--								op_sub after 1800 ns, 
--								op_and after 2000 ns, 
--								op_or after 2200 ns, 
--								op_xor after 2400 ns, 
--                        op_cmpe after 2600 ns,
--								op_cmpl after 2800 ns, 
--								op_cmpg after 3000 ns, 
--								op_ascii2bin after 3200 ns, 
--								op_bin2ascii after 3400 ns,
--								op_oeacc after 3600 ns;
--					wait for 10000 ns;
	 end process ;

END behav;
